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all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. doc. version 0.8 total page 33 date 2007/03/20 product specification 3.5" color tft-lcd module model name: a035qn02 v0 < >preliminary specification < >final specification note: the content of this specification is subject to change . ? 2006 au optronics all rights reserved do not copy. www..net www..net
version 0.8 page: 2/33 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. record of revision version revise date page content 0.0 2006/10/20 first draft. 0.1 2006/10/24 11 e-4-a. update ac timing condition 14 e-5-d. update spi i/f timing condition 23 j-1. add application circuit 24 j-1. add component bom list for the applicatio n circuit 0.2 2006/11/14 4 update module thickness to 4.0mm ( original 4.1mm) 4 add description of gray level inversion 5 update mechanical drawing 6, 7 pin assignment revised from 61 pins to 67 pi ns 10, 11 update power on/off sequence 19 add panel fpc bending test, touch panel fp c peeling test & touch panel impact resistance criteria 22 update the cushion area illustration 24 update application circuit 0.3 2006/11/15 6 correct the pin description, pin 8 dgnd2 agnd1 8 update the led curve 0.4 2006/11/27 5 update the drawing 0.5 2006/12/04 5 update the drawing item original updated fpc thickness 0.3 6 0.05mm 0.2 6 0.03mm module left edge to suggested bezel open area left edg e 2.76mm 2.71mm module left edge to tp a/a left edge 3.16mm 3.11mm module left edge to lcd a/a left edge 3.46mm 3.41mm module upper edge to suggested bezel open area upper edge 2.82mm 2.77mm module upper edge to tp a/a upper edge 3.22mm 3.17m m module upper edge to lcd a/a upper edge 3.52mm 3.47 mm 0.6 2006/12/15 5 update drawing, add label location , size and thickness 0.7 2007/01/29 4 update module dimension (thickness 4mm 4.32mm) 5 update drawing, modify thickness 14 update command register map, add detailed desc riptions 0.8 2007/03/20 5 update the module weight www..net www..net
version 0.8 page: 3/33 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. contents: a. general description ................................ ................................................... .................... 4 b. features ........................................... ................................................... ............................ 4 c. physical specifications............................ ................................................... ................... 5 d. outline dimension.................................. ................................................... ..................... 6 e. electrical specifications .......................... ................................................... ................... 7 1. pin assignment .................................. ................................................... ................................................... .. 7 2. absolute maximum ratings ........................ ................................................... ........................................... 9 3. electrical characteristics ...................... ................................................... ............................................... 10 a. tft- lcd panel (gnd=0v) ......................... ................................................... ................................... 10 b. backlight driving conditions .................... ................................................... ....................................... 10 4. ac timing....................................... ................................................... ................................................... ......11 a. power on/off sequence.............................. ................................................... .......................................11 b. timing condition ................................... ................................................... .......................................... 12 c. timing diagram ..................................... ................................................... .......................................... 13 5. command register map ............................ ................................................... ........................................... 15 a. serial setting map................................. ................................................... ........................................... 15 b. description of serial control data................. ................................................... .................................... 16 f. optical specifications (note 1, 2) ................. ................................................... ............ 25 g. reliability test items ............................. ................................................... .................... 27 h. touch screen panel specifications .................. ................................................... ....... 28 1. fpc pin assignment .............................. ................................................... ............................................... 28 2. electrical characteristics ...................... ................................................... ............................................... 28 3. mechanical characteristics...................... ................................................... ............................................ 28 4. life test condition............................. ................................................... ................................................... . 29 5. attention....................................... ................................................... ................................................... ....... 29 i. packing form....................................... ................................................... ...................... 31 j. application note................................... ................................................... ..................... 32 1. application circuit ................................ ................................................... .............................................. 32 www..net www..net
version 0.8 page: 4/33 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a. general description a035qn02 v0 is an amorphous transmissive type thin film transistor liquid crystal display (tft-lcd). this model is composed of a tft-lcd , a driver, an fpc (flexible printed circuit), a backlight unit and a touch panel. b. features 3.5-inch display with touch panel qvga resolution in rgb stripe dot arrangement dc/dc integrated high brightness 3-wire register setting interfaces: parallel rgb 18-bit wide viewing angle integrated touch screen panel (resistive type) 3-in-1 fpc for lcd signals, backlight led power and to uch panel green design www..net www..net
version 0.8 page: 5/33 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. c. physical specifications no. item unit specification remark 1 display resolution dot 320 rgb (h)240(v) 2 active area mm 70.08(h)52.56(v) 3 screen size inch 3.5(diagonal) 4 dot pitch mm 0.073(h)0.219(v) 5 color configuration -- r. g. b. stripe note 1 6 color depth -- 262k colors 7 overall dimension mm 76.9(h) 63.9(v) 4.32(t) note 2 8 weight g 40 9 panel surface treatment -- hard coating 3h 10 display mode -- normally white 11 gray level inversion direction 6 o?clock note 1: below figure shows dot stripe arrangement. note 2: not including fpc. refer to the drawing nex t page for further information. www..net www..net
version 0.8 page: 6/33 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. d. outline dimension www..net www..net
version 0.8 page: 7/33 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. e. electrical specifications 1. pin assignment connector type: fh26g 67pin 0.3mm pitch connector no. pin name i/o description remarks 1 led_c pi cathode for led back-light 2 led_a pi anode for led back-light 3 dgnd1 g grounding for digital circuit 4 x1 o touch panel right electrode 5 y2 o touch panel bottom electrode 6 x2 o touch panel left electrode 7 y1 o touch panel top electrode 8 agnd1 g grounding for digital circuit 9 vgh c stabilizing capacitor 10 c2p c booster capacitor 11 c2n c booster capacitor 12 c1p c booster capacitor 13 c1n c booster capacitor 14 vgl c stabilizing capacitor 15 c3n c booster capacitor 16 c3p c booster capacitor 17 agnd2 g grounding for analog circuit 18 vcix2 c stabilizing capacitor 19 cyp c booster capacitor 20 cyn c booster capacitor 21 vci pi booster input voltage pin 22 nc n not connected 23 agnd3 g grounding for analog circuit 24 vcim c booster capacitor 25 cxp c booster capacitor 26 cxn c booster capacitor 27 cm i input pinto select 262k- or 8-color mode 28 reset i system reset pin 29 dgnd2 g grounding for digital circuit 30 vddio pi voltage input pin for logic i/o 31 vcore c stabilizing capacitor 32 dgnd3 g grounding for logic i/o www..net www..net
version 0.8 page: 8/33 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. 33 shut i display shut-down pin for sleep-mode 34 csb i chip select pin of serial interface 35 sdi i data input pin in serial mode 36 sck i clock input pin in serial mode 37 vdrop c stabilizing capacitor 38 den i display enable pin from controller 39 bb5 i blue data 40 bb4 i blue data 41 bb3 i blue data 42 bb2 i blue data 43 bb1 i blue data 44 bb0 i blue data 45 gg5 i green data 46 gg4 i green data 47 gg3 i green data 48 gg2 i green data 49 gg1 i green data 50 gg0 i green data 51 rr5 i red data 52 rr4 i red data 53 rr3 i red data 54 rr2 i red data 55 rr1 i red data 56 rr0 i red data 57 vsync i frame synchronization signal 58 hsync i line synchronization signal 59 dotclk i dot-clock and oscillator source 60 cdmuo c stabilizing capacitor 61 dgnd4 g grounding for digital circuit 62 vlcd63 c stabilizing capacitor 63 vcomh c stabilizing capacitor 64 vcoml c stabilizing capacitor 65 dgnd5 g grounding for digital circuit 66 csvcmp c stabilizing capacitor 67 csvcmn c stabilizing capacitor i: digital signal input, o: digital signal output, g: gnd, pi: power input, c: capacitor www..net www..net
version 0.8 page: 9/33 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. 2. absolute maximum ratings values items symbol min. max. unit condition vddio 1.8 3.6 v power voltage vci 2.5 3.6 v vi 0 0.2 x vddio v input signal voltage vi 0.8 x vddio vddio v led reverse voltage vr 2 v one led led forward current if 30 ma one led, note 2 operating temperature (ta) t op -20 70 ? c note 3 storage temperature t st -30 85 ? c note 3 note 1.if the operating condition exceeds the absol ute maximum ratings, the tft-lcd module may be damaged permanently. also, if the module operated w ith the absolute maximum ratings for a long time, its reliability may drop. note 2. if led current exceeds the limit curve, the lifetime will drop dramatically. note 3. 90% rh maximum humidity when temp. 60 ? c. if temp. >60 ? c, the absolute humidity maximum shall be less than 90% rh. www..net www..net
version 0.8 page: 10/33 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. 3. electrical characteristics the following items are measured under stable condi tion and suggested application circuit. a. tft- lcd panel (gnd=0v) parameter symbol min typ max unit notes digital power supply vddio 1.8 3.3 3.6 v analog power supply vci 2.5 3.3 3.6 v frame frequency f frame 60 hz dot data clock dclk 5 mhz note 1. panel surface temperature should be kept le ss than content of section 3.2. ?absolute maximum ratings" b. backlight driving conditions parameter symbol min. typ. max. unit remark led supply current i l 20 ma single serial led supply voltage v l 19.2 v single serial led life time l l 10,000 --- --- hr note 2, 3 note 1: led backlight is six leds serial type. note 2: the ?led supply voltage? is defined by the number of led at ta=25 ? c, i l =20ma. in the case of 6 pcs led, v l =3.2*6=19.2v note 3: the ?led life time? is defined as the time for the module brightness to decrease to 50% of the initial value at ta=25 ? c, i l =20ma note 4: the led lifetime could be decreased if oper ating i l is larger than 25ma www..net www..net
version 0.8 page: 11/33 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. 4. ac timing a. power on/off sequence power on vci vddio resb shut dotclk hsync vsync display on >0ms >1ns tp-shut tclk-shut 1 st 10th tshut-on characteristics symbol min typ max unit vddio on to falling edge of shut tp-shut 1 usec dotclk tclk-shut 1 clk 10 frame falling edge of shut to display on -- 1 line: 336 clk -- 1frame: 244 line -- dotclk = 5.0 mhz tshut-on 164 msec note1: it is necessary to input dotclk before the f alling edge of shut. note2: display starts at 10 th falling edge of vstnc after the falling edge of shu t www..net www..net
version 0.8 page: 12/33 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. power off vci vddio resb shut dotclk hsync vsync led on >1 us >1ns 1 st 2nd tshut-off off toff-vdd characteristics symbol min typ max unit 2 10 frame rising edge of shut to display off -- 1 line: 336 clk -- 1frame: 244 line -- dotclk = 5.0 mhz tshut-off 32.8 msec input-signal-off to v ddext / v ddio off toff-vdd 1 usec note1: dotclk must be maintained at lease 2 frames after the rising edge of shut. note2: display become off at the 2 nd falling edge of vstnc after the falling edge of shu t. note3: if reset signal is necessary for power down, provide it after the 2-frames-cycle of the shut pe riod. b. timing condition characteristics symbol min typ max unit dotclk frequency f dotclk 5.0 7.5 mhz dotclk period t dotclk 133 200 nsec vsync setup time t vsys 20 nsec vsync hold time t vsyh 20 nsec hsync setup time t hsys 20 nsec www..net www..net
version 0.8 page: 13/33 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. hsync hold time t hsyh 20 nsec phase difference of sync signal falling edge t hv 0 320 t dotclk dotclk low period t ckl 66.5 nsec dotclk high period t ckh 66.5 nsec data setup time t ds 40 nsec data hold time t dh 40 nsec reset pulse width t res 10 nsec rise / fall time t r /t f 20 100 nsec c. timing diagram t vsys t vsyh t hsyh t hsys t hv t dotclk t ckl t ckh t ds t dh t r t r / t f vsync hsync dotclk pixel www..net www..net
version 0.8 page: 14/33 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. d0 d1 d318 d319 dummy dummy hdisp = 320 t hbp = 8 t hfp = 8 h cycle = 336 dotclk hysnc den pixel data v cycle = 244 lines vdisp = 240 lines t vbp = 2 t vfp = 2 line 0 line 239 vsync hsync den 0 ms v cycle = 244 lines vdisp = 240 lines t vbp = 2 t vfp = 2 line 0 line 239 vpbp vpdsp vsync hsync den 0 ms note: the falling edge of hsync belongs to blanking period is always behind or equal to the one of vsy nc. www..net www..net
version 0.8 page: 15/33 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. 5. command register map a. serial setting map reg# register r/w d/c ib15 ib14 ib13 ib12 ib11 ib10 ib09 ib08 ib07 ib06 ib05 ib04 ib03 ib02 ib01 ib00 r index 0 0 * * * * * * * * * id6 id5 id4 id3 id2 id1 id0 driver output control 0 1 0 0 rev cad bgr sm tb rl 1 1 1 0 1 1 1 1 r01h [00xx][x0xx]ef 0 0 x x x 0 x x 1 1 1 0 1 1 1 1 lcd drive ac control 0 1 0 0 0 0 0 0 b/c ero 0 nw6 nw5 nw4 nw3 nw2 nw1 nw0 r02h (0300h) 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 power control (1) 0 1 dct3 dct2 dct1 dct0 bt2 bt1 bt0 0 dc3 dc2 dc1 dc0 ap2 ap1 ap0 0 r03h (7272h) 0 1 1 1 0 0 1 0 0 1 1 1 0 0 1 0 frame cycle control 0 1 no1 no0 sdt1 sdt0 eq1 eq0 0 0 0 0 0 0 0 0 0 0 r0bh (dc00h) 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 power control (2) 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 vrc2 vrc1 vrc0 r0ch (0002h) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 power control (3) 0 1 0 0 0 0 0 0 0 0 0 0 0 0 vrh3 vrh2 vrh1 vrh0 r0dh (000ah) 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 power control (4) 0 1 0 0 vcomg vdv4 vdv3 vdv2 vdv1 vdv0 0 0 0 0 0 0 0 0 r0eh (3200h) 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 gate scan starting position 0 1 0 0 0 0 0 0 0 0 scn7 scn6 scn5 scn4 scn3 scn2 scn1 scn0 r0fh (0000h) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 horizontal porch 0 1 xlim8 xlim7 xlim6 xlim5 xlim4 xlim3 xlim2 xlim1 xlim0 0 hbp5 hbp4 hbp3 hbp2 hbp1 hbp0 r16h (9f86h) 1 0 0 1 1 1 1 1 1 0 0 0 0 1 1 0 vertical porch 0 1 0 0 0 0 0 0 0 0 vbp7 vbp6 vbp5 vbp4 vbp3 vbp2 vbp1 vbp0 r17h (0002h) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 power control (5) 0 1 0 0 0 0 0 0 0 0 notp 0 vcm5 vcm4 vcm3 vcm2 vcm1 vcm0 r1eh (002dh) 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 3 gamma 0 1 1 0 1 1 1 0 0 1 0 1 0 0 0 1 0 olo r2eh (b945h) 1 0 1 1 1 0 0 1 0 1 0 0 0 1 0 1 control (1) 0 1 0 0 0 0 0 pkp12 pkp11 pkp12 0 0 0 0 0 pkp02 pkp01 pkp00 r30h (0000h) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 control (1) 0 1 0 0 0 0 0 pkp32 pkp31 pkp32 0 0 0 0 0 pkp22 pkp21 pkp20 r31h (0200h) 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 control (1) 0 1 0 0 0 0 0 pkp52 pkp51 pkp52 0 0 0 0 0 pkp42 pkp41 pkp40 r32h (0001h) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 control (1) 0 1 0 0 0 0 0 prp12 prp11 prp12 0 0 0 0 0 prp02 prp01 prp00 r33h (0700h) 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 www..net www..net
version 0.8 page: 16/33 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. control (1) 0 1 0 0 0 0 0 pkn12 pkn11 pkn12 0 0 0 0 0 pkn02 pkn01 pkn00 r34h (0405h) 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 control (1) 0 1 0 0 0 0 0 pkn32 pkn31 pkn32 0 0 0 0 0 pkn22 pkn21 pkn20 r35h (0202h) 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 control (1) 0 1 0 0 0 0 0 pkn52 pkn51 pkn52 0 0 0 0 0 pkn42 pkn41 pkn40 r36h (0707h) 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 control (1) 0 1 0 0 0 0 0 prn12 prn11 prn12 0 0 0 0 0 prn02 prn01 prn00 r37h (0006h) 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 control (2) 0 1 0 0 0 vrp14 vrp13 vrp12 vrp11 vrp10 0 0 0 0 vrp03 vrp02 vrp01 vrp00 r3ah (0700h) 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 control (2) 0 1 0 0 0 vrn14 vrn13 vrn12 vrn11 vrn10 0 0 0 0 vrn03 vrn02 vrn01 vrn00 r3bh (0003h) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 b. description of serial control data driver output control 0 1 0 0 rev cad bgr sm tb rl 1 1 1 0 1 1 1 1 r01h [00xx][x0xx]ef 0 0 x x x 0 x x 1 1 1 0 1 1 1 1 rev: displays all character and graphic display sections with reversal when rev = ?1?. since the grayscale level can be reversed, display of the same data is enabled on normally white and n ormally black panels. source output level is indicated below. source output level rev rgb data vcom = ?h? vcom = ?l? 1 000000b : 111111b v63 : v0 v0 : v63 0 000000b : 111111b v0 : v63 v63 : v0 cad: set up based on retention capacitor configuration o f the tft panel. cad retention capacitor configuration 0 cs on common 1 cs on gate bgr: selects the arrangement. when bgr = ?0? color is assigned from s0. when bgr = ?1? color is assigned from s0 . sm: change the division of gate driver. www..net www..net
version 0.8 page: 17/33 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. when sm = ?0?, odd/even division (interlace mode) i s selected. when sm = ?1?, upper/lower division is selected. select the division mode according to the mounting method. tb: selects the output shift direction of the gate driv er. when tb = ?1?, g0 shifts to g239. when tb = ?0?, g2 39 shifts to g0. rl: selects the output shift direction of the source dr iver. when rl = ?1?, s0 shifts to s959 and colo r is assigned from s1. when rl = ?0?, s959 shifts to s0 and colo r is assigned from s959. set rl bit and bgr bit when changing the dot order of r, g and b. note: the default setting of register bits rev , cad , bgr , tb and rl are defined by the logic stage of corresponding ha rdware pins. these bits will override the hardware setting once software command was sent to set the bits. lcd drive ac control 0 1 0 0 0 0 0 0 b/c ero 0 nw6 nw5 nw4 nw3 nw2 nw1 nw0 r02h (0300h) 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 b/c: select the liquid crystal drive waveform vcom. when b/c = 0, frame inversion of the lcd driving si gnal is enabled. when b/c = 1, a n-line inversion waveform is genera ted and alternates in a n-line equals to nw[7:0]+1. eor: when b/c = 1 and eor = 1, the odd/even frame-select signals and the n-line inversion signals are eored for alternating drive. eor is used when the lcd is not alternated by combi ning the set values of the lines of the lcd driven and the n-lines. nw6-0: specify the number of lines that will alternate at the n-line inversion setting (b/c = 1). nw6-0 alter nate for every set value + 1 lines. power control (1) 0 1 dct3 dct2 dct1 dct0 bt2 bt1 bt0 0 dc3 dc2 dc1 dc0 ap2 ap1 ap0 0 r03h (7272h) 0 1 1 1 0 0 1 0 0 1 1 1 0 0 1 0 dct3-0: set the step-up cycle of the step-up circuit for 8- color mode (cm = vddio). when the cycle is accelerated, the driving ability of the step-up circuit increases, but its current c onsumption increases too. adjust the cycle taking into account the display qu ality and power consumption. dct3 dct2 dct1 dct0 step-up cycle 0 0 0 0 fline 14 0 0 0 1 fline 12 0 0 1 0 fline 8 0 0 1 1 fline 7 0 1 0 0 fline 6 0 1 0 1 fline 5 0 1 1 0 fline 4 0 1 1 1 fline 3 1 0 0 0 fline 2 www..net www..net
version 0.8 page: 18/33 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. 1 0 0 1 fline 1 1 0 1 0 fosc / 64 1 0 1 1 fosc / 80 1 1 0 0 fosc / 96 1 1 0 1 fosc / 128 1 1 1 0 fosc / 160 1 1 1 1 fosc / 256 bt2-0: control the step-up factor of the step-up circuit. adjust the step-up factor according to the power-su pply voltage to be used. bt2 bt1 bt0 v gh output v gl output v gh booster ratio v gl booster ratio 0 0 0 v cix2 x3 -( v cix2 x3)+vci 6 -5 0 0 1 v cix2 x3 -( v cix2 x2) 6 -4 0 1 0 v cix2 x3 -( v cix2 x3) 6 -6 0 1 1 v cix2 x2+vci -( v cix2 x3)+vci 5 -5 1 0 0 v cix2 x2+vci -( v cix2 x2) 5 -4 1 0 1 v cix2 x2+vci -( v cix2 x2)+vci 5 -3 1 1 0 v cix2 x2 -( v cix2 x2) 4 -4 1 1 1 vcix2x2 -( v cix2 x2)+vci 4 -3 dc3-0: set the step-up cycle of the step-up circuit for 26 2k-color mode (cm = vss). when the cycle is accelerated, the driving ability of the step-up circuit increases, but its current c onsumption increases too. adjust the cycle taking into account the display qu ality and power consumption. dc3 dc2 dc1 dc0 step-up cycle 0 0 0 0 fline 14 0 0 0 1 fline 12 0 0 1 0 fline 8 0 0 1 1 fline 7 0 1 0 0 fline 6 0 1 0 1 fline 5 0 1 1 0 fline 4 0 1 1 1 fline 3 1 0 0 0 fline 2 1 0 0 1 fline 1 1 0 1 0 fosc / 64 1 0 1 1 fosc / 80 1 1 0 0 fosc / 96 www..net www..net
version 0.8 page: 19/33 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. 1 1 0 1 fosc / 128 1 1 1 0 fosc / 160 1 1 1 1 fosc / 256 ap2-0: adjust the amount of current from the stable-curren t source in the internal operational amplifier circ uit. when the amount of current becomes large, the drivi ng ability of the operational-amplifier circuits in crease. adjust the current taking into account the power co nsumption. during times when there is no display, such as when the system is in a sleep mode. ap2 ap1 ap0 op-amp power 0 0 0 least 0 0 1 small 0 1 0 small to medium 0 1 1 medium 1 0 0 medium to large 1 0 1 large 1 1 0 large to maximum 1 1 1 maximum frame cycle control 0 1 no1 no0 sdt1 sdt0 eq1 eq0 0 0 0 0 0 0 0 0 0 0 r0bh (dc00h) 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 no1-0: sets amount of non-overlap of the gate output. sdt1-0: set delay amount from the gate output signal fallin g edge of the source outputs. eq1-0: sets the equalizing period on source power control (2) 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 vrc2 vrc1 vrc0 r0ch (0002h) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 vrc[2:0]: adjust vcix2 output voltage. the adjusted level is indicated in the chart below vrc2-0 setting. vrc2 vrc1 vrc0 v cix2 voltage 0 0 0 5.1v 0 0 1 5.3v 0 1 0 5.5v 0 1 1 5.7v 1 0 0 5.9v 1 0 1 6.1v 1 1 0 reserved 1 1 1 reserved www..net www..net
version 0.8 page: 20/33 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. power control (3) 0 1 0 0 0 0 0 0 0 0 0 0 0 0 vrh3 vrh2 vrh1 vrh0 r0dh (000ah) 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 vrh3-0: set amplitude magnification of vlcd63. these bits a mplify the vlcd63 voltage 1.78 to 3.00 times the vr ef voltage set by vrh3-0. vrh3 vrh2 vrh1 vrh0 v lcd63 voltage 0 0 0 0 vref x 2.815 0 0 0 1 vref x 2.905 0 0 1 0 vref x 3.000 0 0 1 1 vref x 1.780 0 1 0 0 vref x 1.850 0 1 0 1 vref x 1.930 0 1 1 0 vref x 2.020 0 1 1 1 vref x 2.090 1 0 0 0 vref x 2.165 1 0 0 1 vref x 2.245 1 0 1 0 vref x 2.335 1 0 1 1 vref x 2.400 1 1 0 0 vref x 2.500 1 1 0 1 vref x 2.570 1 1 1 0 vref x 2.645 1 1 1 1 vref x 2.725 power control (4) 0 1 0 0 vcomg vdv4 vdv3 vdv2 vdv1 vdv0 0 0 0 0 0 0 0 0 r0eh (3200h) 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 vcomg: when vcomg = ?1?, it is possible to set output volt age of vcoml to any level, and the instruction (vdv 4-0) becomes available. when vcomg = ?0?, vcoml output is fixed to hi-z lev el, vci2 output for vcoml power supply stops, and t he instruction (vdv4-0) becomes unavailable. set vcomg according to the sequence of power supply setting flow as it relates with power supply opera ting sequence. vdv4-0: set the alternating amplitudes of vcom at the vcom alternating drive. these bits amplify vcom amplitude 0.6 to 1.23 times the vlcd63 voltage. when vcomg = ?0?, the settings become invalid. vdv4 vdv3 vdv2 vdv1 vdv0 vcoma 0 0 0 0 0 vlcd63 x 0.60 0 0 0 0 1 vlcd63 x 0.63 : : step = 0.03 www..net www..net
version 0.8 page: 21/33 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. : 0 1 1 0 1 vlcd63 x 0.99 0 1 1 1 0 vlcd63 x 1.02 0 1 1 1 1 reserved 1 0 0 0 0 vlcd63 x 1.05 1 0 0 0 1 vlcd63 x 1.08 : : : step = 0.03 1 0 1 0 1 vlcd63 x 1.20 1 0 1 1 0 vlcd63 x 1.23 1 0 1 1 1 reserved 1 1 * * * reserved vcomas: set the equation of vcoml. v coml = x v comh - v coma vcomas 0 0.94 1 0.5 gate scan starting position 0 1 0 0 0 0 0 0 0 0 scn7 scn6 scn5 scn4 scn3 scn2 scn1 scn0 r0fh (0000h) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 scn7-0: set the scanning starting position of the gate driv er. horizontal porch 0 1 xl8 xl7 xl6 xl5 xl4 xl3 xl2 xl1 xl0 0 hbp5 hbp4 hbp3 hbp2 hbp1 hbp0 r16h (9f86h) 1 0 0 1 1 1 1 1 1 0 0 0 0 1 1 0 xl7-0: set the number of valid pixel per line. xl8 xl7 xl6 xl5 xl4 xl3 xl2 xl1 xl0 # of pixels per line 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 2 0 0 0 0 0 0 0 1 0 3 : : : : step = 1 : 1 0 0 1 1 1 1 1 0 319 1 0 0 1 1 1 1 1 320 www..net www..net
version 0.8 page: 22/33 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. 1 0 1 * * * * * * reserved 1 1 * * * * * * * reserved hbp5-0: set the delay period from falling edge of hsync sig nal to first valid data. the pixel data exceed the range set by xl8-0 and be fore the first valid data will be treated as dummy data. hbp5 hbp4 hbp3 hbp2 hbp1 hbp0 # of clock cycle of dotclk 0 0 0 0 0 0 2 0 0 0 0 0 1 3 0 0 0 0 1 0 4 : : : : step = 1 : 1 1 1 1 1 0 64 1 1 1 1 1 1 65 d0 d1 d318 d319 dummy dummy default 320 pixels per line set by hbp5 - 0 8 dotclk cycle time of hync hsync pixel data dotclk vertical porch 0 1 0 0 0 0 0 0 0 0 vbp7 vbp6 vbp5 vbp4 vbp3 vbp2 vbp1 vbp0 r17h (0002h) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 vbp7-0: set the delay period from falling edge of vsync to first valid line. the line data within this delay period will be trea ted as dummy line. vbp7 vbp6 vbp5 vbp4 vbp3 vbp2 vbp1 vbp0 vbp7 # of pixels per line 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 2 0 0 0 0 0 0 0 1 0 3 www..net www..net
version 0.8 page: 23/33 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. : : : : step = 1 : 1 0 0 1 1 1 1 1 0 319 1 0 0 1 1 1 1 1 320 1 0 1 * * * * * * reserved 1 1 * * * * * * * reserved cycle time of vsync vdisp = 240 set by vbp 7 - 0 2 dummy line 0 line 239 vsync hsync power control (5) 0 1 0 0 0 0 0 0 0 0 notp 0 vcm5 vcm4 vcm3 vcm2 vcm1 vcm0 r1eh (002dh) 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 notp: notp equals to ?0? after power on reset and vcomh v oltage equals to programmed otp value. when notp set to ?1?, setting of vcm5-0 becomes val id and voltage of vcomh can be adjusted. vcm5-0: set the vcomh voltage if notp = ?1?. these bits amp lify the vcomh voltage 0.36 to 0.99 times the vlcd6 3 voltage. 3 gamma 0 1 1 0 1 1 1 0 0 1 0 1 0 0 0 1 0 olo r2eh (b945h) 1 0 1 1 1 0 0 1 0 1 0 0 0 1 0 1 olo: when olo = ?1?, all r,g and b gamma registers are s et by one set of gamma control, r30h to r3bh. when olo = ?0?, r, g and b gamma registers are set separately by registers r30h to r3bh, r40h to r4bh and r50h to r5bh. control (1) 0 1 0 0 0 0 0 pkp12 pkp11 pkp12 0 0 0 0 0 pkp02 pkp01 pkp00 r30h (0000h) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 control (1) 0 1 0 0 0 0 0 pkp32 pkp31 pkp32 0 0 0 0 0 pkp22 pkp21 pkp20 r31h (0200h) 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 control (1) 0 1 0 0 0 0 0 pkp52 pkp51 pkp52 0 0 0 0 0 pkp42 pkp41 pkp40 r32h (0001h) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 control (1) 0 1 0 0 0 0 0 prp12 prp11 prp12 0 0 0 0 0 prp02 prp01 prp00 r33h (0700h) 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 www..net www..net
version 0.8 page: 24/33 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. control (1) 0 1 0 0 0 0 0 pkn12 pkn11 pkn12 0 0 0 0 0 pkn02 pkn01 pkn00 r34h (0405h) 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 control (1) 0 1 0 0 0 0 0 pkn32 pkn31 pkn32 0 0 0 0 0 pkn22 pkn21 pkn20 r35h (0202h) 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 control (1) 0 1 0 0 0 0 0 pkn52 pkn51 pkn52 0 0 0 0 0 pkn42 pkn41 pkn40 r36h (0707h) 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 control (1) 0 1 0 0 0 0 0 prn12 prn11 prn12 0 0 0 0 0 prn02 prn01 prn00 r37h (0006h) 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 when olo = ?0?, r30h-r3bh are registers to adjust t he gamma register values on the output of source s( 3n), where n = 0 to 319. s(3n) are the red color source output when bgr = ?0?. when olo = ?1?, r30h-r3bh are registers to adjust t he gamma register values on the output of all sourc e s0 to s959. pkp52?00: gamma micro adjustment register for the positive po larity output. prp12-00: gradient adjustment register for the positive polar ity output. pkn52-00: gamma micro adjustment register for the negative po larity output. prn12-00: gradient adjustment register for the negative polar ity output . control (2) 0 1 0 0 0 vrp14 vrp13 vrp12 vrp11 vrp10 0 0 0 0 vrp03 vrp02 vrp01 vrp00 r3ah (0700h) 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 control (2) 0 1 0 0 0 vrn14 vrn13 vrn12 vrn11 vrn10 0 0 0 0 vrn03 vrn02 vrn01 vrn00 r3bh (0003h) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 vrp14-00: adjustment register for amplification adjustment of the positive polarity output. vrn14-00: adjustment register for the amplification adjustmen t of the negative polarity output. www..net www..net
version 0.8 page: 25/33 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. f. optical specifications (note 1, 2) item symbol condition min. typ. max. unit remark response time rise fall tr tf =0 ? - - 10 15 20 25 ms ms note 3 contrast ratio cr at optimized viewing angle 150 300 - note 5, 6 viewing angle top bottom left right cr R 10 35 40 45 45 50 55 60 60 - - - - deg. note 7, 8 brightness y l =0 ? 280 330 - cd/m 2 note 9 ntsc 50 60 % x =0 ? 0.26 0.31 0.36 white chromaticity y =0 ? 0.28 0.33 0.38 luminance uniformity 75 80 % note 9 note 1: measurement should be performed in the dark room, optical ambient temperature =25 ? c, and backlight current i l =20 ma note 2: to be measured on the center area of panel with a field angle of 1by topcon luminance meter b m-7, after 10 minutes operation. note 3: definition of response time: the output signals of photo detector are measured when the input signals are changed from ?black? to ?white?(falling time) and from ?white? to ?black ?(rising time), respectively. s i g n a l ( r e l a t i v e v a l u e ) "black" tr tf "white" "white" 0% 10% 90% 100% note 4. from liquid crystal characteristics, respon se time will become slower and the color of panel w ill become darker when ambient temperature is below 25 . note 5. contrast ratio is calculated with the follo wing formula. www..net www..net
version 0.8 page: 26/33 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. note 6. white vi=vi50 1.5v black vi=vi50 2.0v ? ? means that the analog input signal swings in phas e with com signal. ? ? means that the analog input signal swings out of p hase with com signal. vi50 :the analog input voltage when transmission is 50% the 100% transmission is defined as the transmissio n of lcd panel when all the input terminals of module are electrically opened. note 7. definition of viewing angle: refer to figur e as below. note 8. the viewing angles are measured at the cent er area of the panel when all the input terminals o f lcd panel are electrically opened. note 9. definition of brightness and luminance unif ormity: brightness = average brightness of nine points illu strated below min. brightness of nine poin ts max. brightness of nine points 9 8 7 6 5 4 3 2 state black" " at is lcd when output detector photo state white" " at is lcd when output detector photo tio contrastra = luminance uniformity = www..net www..net
version 0.8 page: 27/33 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. g. reliability test items no. test items conditions remark 1 high temperature storage ta= 85 240hrs 2 low temperature storage ta= -30 240hrs 3 high temperature operation ta= 70 240hrs 4 low temperature operation ta= -20 240hrs 5 high temperature & high humidity ta= 60 . 90% rh 240hrs operation 6 heat shock -25 ~70 , 50 cycle, 2hrs/cycle non-operation 7 electrostatic discharge contact 6 4kv, air +/-12kv display surface non-operation 8 vibration (with carton) random vibration: 0.015g 2 /hz from 5~200hz ?6db/octave from 200~500hz iec 68-34 9 drop (with carton) height: 60cm 1 corner, 3 edges, 6 surfaces 10 fpc bending test curved radius: 2mm pulling force: 250g bending angle: 180 ? 270 ? 90 ? 180 ? 50 cycles (note 10) 11 touch panel fpc peeling test 5n min peeling upward by 90 ? 12 touch panel impact resistance 11mm(5g) steel ball distance: 70cm measured at the center of touch panel ( touch panel is supported around its four edges with 10mm thick and 10 mm wide pvc board) note 1: in the standard conditions, there is not di splay function ng issue occurred. all the cosmetic specification is judged before the reliability stre ss. note 2: ta: ambient temperature. note 3: bending test condition: 180? 270? 90? www..net www..net
version 0.8 page: 28/33 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. h. touch screen panel specifications 1. fpc pin assignment pin no. symbol i/o 4 r o 5 b o 6 l o 7 u o 2. electrical characteristics item min. max. unit remark rate dc voltage 7 v x (film) 350 950 resistance y (glass) 150 800 at connector linearity -1.5% 1.5% -- note 1, test by 250 gf chattering 10 ms at connector pin insulation resistance 10m dc 25v note 1: measurement condition of linearity: differe nce between actual voltage & theoretical voltage is an error at any points. linearity is the value max. error voltage divided by voltage difference on active area. 3. mechanical characteristics item min. max. unit remark hardness of surface 3 -- h jis k-5400 operation force (pen or finger) -- 50 gf note 1 note 1: within ?guaranteed active area?, but not on the edge and dot-spacer. www..net www..net
version 0.8 page: 29/33 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. 4. life test condition item min. max. unit remark notes life 10 5 -- words note 1, 2 input life 10 6 -- times note 1, 3 note 1: measurement condition of operation force: w ithin ?guaranteed active area?. resistance, insulation resistance, and operation force should b e under 5.2 & 5.3 condition. when user pushes down on the film, resistance between x & y axis mus t be equal or lower than 2k ? . below is test figure. note 2: notes life test condition (by pen): notes a rea for pen notes life test is 109 mm. size of wor d is 7.56.75mm. word is any a.b.c?.. letter. writing spe ed is 60mm/s. center of each word is changed at random in notes area. note 3: input life test condition( by finger): by s ilicone rubber tapping at same point. tapping load is 200g, and tapping frequency is 5hz. 5. attention please pay attention for below matters at mounting design of touch panel of lcd module. 1. do not design enclosure pressing the view area t o prevent from miss input. 2. enclosure support must not touch with view area. 3. use elastic or non-conductive material to enclos ure touch panel. www..net www..net
version 0.8 page: 30/33 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. 4. do not bond film of touch panel with enclosure. 5. the touch panel edge is conductive. do not touch it with any conductive part after mounting. 6. if user wants to cleaning touch panel by air gun , pressure 2kg/cm2 below is suggested. not to blow glass from fpc site to prevent fpc peeled off. 7. do not put a heavy shock or stress on touch pane l and film surface. ex. don?t lift the panel by fil m face with vacuum. 8. do not lift lcd module by fpc. 9. please use dry cloth or soft cloth with neutral detergent (after wring dry) or one with ethanol at cleaning. do not use any organic solvent, acid or alkali liqu or. 10. do not pile touch panel. do not put heavy goods on touch panel. recommendation of the cushion area: www..net www..net
version 0.8 page: 31/33 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. i. packing form model(a035qn02) a u o a u o a u o a u o a u o a u o a u o www..net www..net
version 0.8 page: 32/33 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. j. application note 1. application circuit the folowing drawing is the application circuit recommen ded. reset cm bb2 rr1 rr5 gg3 den rr0 bb1 rr4 bb5 gg2 dotclk sck bb0 rr3 bb4 gg1 sdi hsync gg5 bb3 rr2 csb gg0 gg4 vsync shut led_c vcore c2p vgl c2p c1p vddio c1n cyn vgh cdmuo c3n vcix2 c2n c1p c1n c3p vdrop vgh cyp vci c2n c3p vgl led_a c3n dgnd agnd vcix2 cyp vci cyn agnd vcim cxn cxp cxn cxp vcim cdmuo vdrop vcore vddio dgnd vlcd63 vcomh vcoml vcomh vlcd63 vcoml csvcmp csvcmn csvcmp csvcmn dgnd dgnd dgnd dgnd j1a conn 67 60 59 58 57 56 55 54 53 52 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 51 61 62 63 64 65 66 67 60 59 58 57 56 55 54 53 52 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 51 61 62 63 64 65 66 67 c14 2.2uf/6.3v c13 2.2uf/6.3v c17 2.2uf/6.3v c16 2.2uf/6.3v c15 2.2uf/6.3v c18 2.2uf/16v c4 0.22uf/16v c5 0.22uf/6.3v c1 2.2uf/6.3v c3 2.2uf/16v c8 2.2uf/6.3v c12 2.2uf/6.3v c10 2.2uf/6.3v c2 2.2uf/6.3v c7 0.22uf/16v c9 0.22uf/6.3v c6 2.2uf/16v c11 0.22uf/6.3v to led current supplier reserve for touch panel analog power input logic i/o power input www..net www..net
version 0.8 page: 33/33 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. the bom list is as follows. name component value description remark j1a 61 pins connector c1 capacitor 2.2uf 6.3v / x5r c2 capacitor 2.2uf 6.3v / x5r c3 capacitor 2.2uf 16v / x5r c4 capacitor 0.22uf 16v / x5r c5 capacitor 0.22uf 6.3v / x5r c6 capacitor 2.2uf 16v / x5r c7 capacitor 0.22uf 16v / x5r c8 capacitor 2.2uf 6.3v / x5r c9 capacitor 0.22uf 6.3v / x5r c10 capacitor 2.2uf 6.3v / x5r c11 capacitor 0.22uf 6.3v / x5r c12 capacitor 2.2uf 6.3v / x5r c13 capacitor 2.2uf 6.3v / x5r c14 capacitor 2.2uf 6.3v / x5r c15 capacitor 2.2uf 6.3v / x5r c16 capacitor 2.2uf 6.3v / x5r c17 capacitor 2.2uf 6.3v / x5r c18 capacitor 2.2uf 6.3v / x5r www..net www..net

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